`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    21:03:37 12/01/2020 
// Design Name: 
// Module Name:    CMP 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

include "defines.v";

module CMP(
    input [31:0] A1,
    input [31:0] A2,
    input [4:0] CmpOp,
    output reg zero
    );
	always @*
	begin
		case (CmpOp)
			`cmpEQ:
				zero <= (A1 == A2); 
			`cmpNE:
				zero <= (A1 != A2);
			`cmpLEZ:
				zero <= ($signed(A1) <= 0);
			`cmpGTZ:
				zero <= ($signed(A1) > 0);
			`cmpLTZ:
				zero <= ($signed(A1) < 0);
			`cmpGEZ:
				zero <= ($signed(A1) >= 0);
			default:
				zero <= 0;
		endcase
	end
	
endmodule
